The power used to drive a clock distribution system in an integrated circuit chip represents a large portion of the total system power. Resonant clocking is a technique that may be used to reduce the power required to drive the clock distribution system, and thereby reduce the total system power, by recycling energy with a resonant clock network. Resonant clocking may be achieved using a coupled LC oscillator circuit in which an inductor (represented by inductance L) recycles power for use in clocking the driven circuit (represented by capacitance C). However, LC-based resonant clocking has the following shortcomings: it is limited to a narrow operating frequency range; it provides a slow slew rate of the clock waveform (e.g., a sine wave instead of a square wave); and it requires a large on-chip area to accommodate the inductor of the LC oscillator.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.